The present invention relates generally to memory devices, and more particularly to memory devices that require periodic refresh signals to maintain their data contents, such as synchronous dynamic random access memory (SDRAM) devices.
SDRAM consists of an array of capacitive cells having a voltage that degrades over time as a function of the capacitance and the internal device resistance at the cells terminals, referred to as the time constant of the circuit, or 1/RC. As the voltage of a cell degrades over time from its nominal voltage, the voltage will decrease into a transition region wherein the equivalent binary data bit value represented by that voltage value is indeterminate; i.e. the data bit value is neither a binary ‘0’ or a binary ‘1’. Eventually the voltage will degrade to zero, and thus, SDRAMs require periodic refresh signals from a host memory controller to recharge the cells to nominal voltage levels. SDRAMs may lose data, even if the SDRAMS have backup power from a battery, if the host memory controller loses power and ceases issuing refresh signals. However, at least some known host memory controllers consume more electrical power than may be practically supplied by a backup battery.